Due to improper manufacturing, integrated circuits (ICs) are subject to a variety of failure modes. Therefore, each IC must be tested to identify any defective circuits before assembly and shipment. However, both the complexity and the cost of testing an IC are growing rapidly, since ICs having over 100,000 logic gates and 256 pins are now common. At present, there is no sign that this rapid growth rate in complexity will abate.
Even though many techniques and software tools are becoming available to increase design productivity, test productivity lags far behind. Poor test productivity means that the design cycle may soon be dominated by the testing activities. In addition, the complexity of the IC requires both expensive testers (i.e. those costing in excess of a million dollars), and longer test throughput times, thereby driving test costs even higher. In response to this development, and aiming at improving test productivity and reducing test costs, the "IDDQ testing" technique is developed. Benefits of IDDQ testing are discussed in "Zero Defects or Zero Stuck-At Faults--CMOS IC Process Improvements with IDDQ", by J. Soden et al, Proc. Int'l Test Conf., 1990, pp. 255-56 and "Why IDDQ", by S. McEuen, Proc. Int'l Test Conf., 1990, p. 252.
In IDDQ testing, the amount of current (IDD) the IC draws is measured on many, possibly all, test patterns applied to it. Each such measurement is made when the IC is in its quiescent state, i.e. after the circuit has had time to stabilize after switching. These test patterns may exceed tens of thousands of test vectors. IDDQ testing assumes that many IC manufacturing defects cause IDD to be abnormally high. One example is where two circuit nodes are shorted. IDDQ testing is also applicable for detecting many other defects, even open-circuit signal lines in CMOS, as noted in "Testing Oriented Analysis of CMOS ICs With Opens", by W. Maly et al., Proc. Int'l Conference on Computer Aided Design, 1988, pp. 344-47.
IDDQ testing is particularly applicable to circuits of CMOS, BiCMOS and other technologies that have low quiescent current. The circuits of these technologies may have a relatively high current requirement during switching, but typically have a low quiescent current after the circuit stabilizes. Since a defective circuit may cause the current drawn to increase by orders of magnitude from the normal quiescent current, IDDQ testing differentiates such defective circuits from the good circuits. However, the time required for IDDQ testing using this approach is impractical because parametric measurement units (PMUs) in conventional testers cannot provide quickly enough the many accurate current measurements demanded by IDDQ testing. For example, each IDDQ measurement may take from one to ten milliseconds. That is, if 20,000 test vectors are applied, the test time required to complete the test will be between 20 and 200 seconds, which is much too long to be practical for production testing purpose. Hence, specially designed circuits and current probes external to the IC under test have been provided in order to improve throughput time of the IDDQ test. Such techniques are reviewed in "A New Approach to Dynamic IDD Testing", by M. Keating and D. Meyer, Proc. Int'l Test Conf., 1987, pp. 316-21. However, this review did not propose integrating these circuits into the IC. In fact, for the circuits shown therein, both the need for large decoupling capacitors and the high impedance such circuits necessarily add to the ground and power bus lines of the IC make it difficult, if not impossible, to integrate such circuits on-chip without impacting the IC's performance in its target application.
FIGS. 1 and 2 are used to illustrate the IDDQ measurements described above. FIG. 1 is a simplified schematic of an IC 1 showing connection pads 2 and 3 for power (VDD), and connection pads 4 and 5 for ground (VSS). In the following description, the pads, such as 2 and 5, which are connected to the power supply during normal operation are designated "primary power supply pads." Also shown are input pads 6 and 10 and output pads 7 and 16. Output pad 16 is driven by output inverting buffer 17, which is in turn driven at its input lead by the circuit-under-test (CUT) 13. Output pad 16 is connected by a pull-up resistor 18 to the VDD supply. This pull-up resistor 18 is especially useful if inverting buffer 17 can assume a high-impedance state. Output pad 7 of FIG. 1 is driven by an output buffer comprising the PMOS transistor 8 and the NMOS transistor 9, which are respectively pull-up and pull-down transistors to the VDD and VSS supplies. The gates of the NMOS and PMOS transistors 8 and 9 are driven by the CUT 13. Input pad 6 has a pull-up resistor 11 to VDD and drives into the CUT 13. Similarly, input pad 10 has a pull-down resistor 12 to VSS and drives into the CUT 13. Significantly, resistors 11, 12 and 18, output buffer 17, and output buffer formed by transistors 8 and 9 are commonly found devices associated with input and output pads.
FIG. 2 shows the circuit of FIG. 1 being connected to a tester to measure IDDQ. As shown in Figure 2, VSS pads 4, 5 are connected directly to the tester ground 20. VDD pads 2, 3 are both connected to the tester input channel 26, a sense resistor 21, relay 25 and decoupling (or bypass) capacitor 22. During normal functional testing, relay 25 is closed, making a low-impedance connection to the tester power supply 23 (i.e. resistor 21 is shunted). However, during IDDQ testing, relay 25 is opened, forcing the current to flow through sense resistor 21. When the CUT 13 switches, however, the sense resistor 21 is often too large to provide the current necessary to operate CUT 13. A bypass capacitor 22 must therefore be used to supply the necessary operating current during switching. This bypass capacitor 22 is selected to be at least an order of magnitude greater than the sum total of the capacitance on the IC and driven by the IC. For example, if all the switching circuits, including the output buffers, must drive a total of 0.05 uF, then the decoupling capacitor 22 should be at least 0.5 uF. If this 10:1 ratio is used, the worst case "voltage droop" at the VDD pads would be 0.5 V in a circuit using a 5.0 volt power supply. The quiescent current after switching is measured at test channel 26 (input to a tester) by the voltage drop across the sense resistor 21. In this configuration, a tester channel 26 is dedicated to measure the IDD current.
The operating speed of such a measurement system is determined by the relative sizes of the sense resistor (R) 21, the decoupling capacitor (C) 22, the maximum permissible "voltage droop", and the resolution of the voltage measurement system. For example, if the test channel 26 is a standard tester input logic channel, it might be decided that it is reasonable to make a measurement with an accuracy of better than 100 mV. This would then be VDD-0.1 volts, or 4.9 V, on a 5.0 V circuit. If the maximum "voltage droop" permissible is 0.5 V, then the current through resistor 21 must have sufficient time to restore the voltage on decoupling capacitor 22 to at least 4.9 V on the worst case "good" circuit before quiescent current for each test vector can be measured. In this example, if we consider a current measuring in excess of 100 uA through sense resistor 21 as indicative of a "bad" circuit, we need a resistor value of about 1 k ohms to detect the 100 uA as a voltage difference of 0.1 volts across the resistor. Assuming the good circuit draws less than 1 uA, then the time to charge decoupling capacitor 22 from 4.5 V to 4.9 V is about 1.6 RC (=1.6.times.1,000.times.0.5.times.10.sup.-6), or 0.8 milliseconds. For a test using 10,000 test vectors, the total test time required would be at least 8 seconds, which is barely acceptable. However, for a test using 100,000 test vectors, the total test time would be an unacceptable 80 seconds.
This method, therefore, is only suitable when either (i) the circuit is to be tested with only a small number of test vectors;, (ii) the circuit has little capacitive loading, or (iii) when a small sense resistor can be used, such as when only defects causing large currents are to be detected.
Practical compromises between accuracy and testing speed must often be made. If the charge on the decoupling capacitor 22 can be supplied through an independent low-impedance source that could be quickly disconnected from the circuit after the circuit switches, test performance would be significantly enhanced. The relay 25 is not adequate for this as relay response times are typically in the millisecond range.
In the reference above, Keating describes having a sense resistor bypassed by a field effect transistor (FET) switch rather than a relay. This technique is illustrated in FIG. 2, which shows as an alternative to relay 25 FET 24 (enclosed in dotted lines) connected across sense resistor 21. Note that because the large decoupling capacitor 22 is needed, Keating does not expect to integrate into the IC under test this IDDQ circuit, which includes FET 24, sense resistor 21, and capacitor 22. Such per se integration is also undesirable because the FET 24 and the sense resistor 21 will each be in series with the VDD bus of the IC, such that their individual impedance will be affecting the speed and power performance of the circuit during functional operation.
Another approach, called "Built-in current (BIC) testing" has been proposed. Under this approach, a special on-chip circuit is used to provide a virtual ground potential to which the rest of the IC is grounded. Current is measured as it flows from the circuit through the virtual ground to the real ground. This procedure and a circuit implementing this procedure are described in "Built-In Current Testing-Feasibility Study" by W. Maly and P. Nigh, Proc. Int'l Conference on Computer Aided Design 1988, pp 340-343. This technique improves the testing speed since the current is measured by an on-chip circuit rather than using an external circuit. However, the circuit described by Maly and Nigh does not provide a quality ground signal. Thus, the performance of the IC suffers because of test purposes. Generally, this is an unacceptable compromise.
Ideally, on-chip circuitry should be used for IDDQ testing without trading-off accuracy and test speed. The BIC technique proposed by Maly above, for example, is unsatisfactory because bus lines in an integrated circuit using the BIC technique are required to be actively driven, thereby causing undue performance degradation during normal use.